1. Field of the Invention
The present invention relates to a semiconductor integrated circuit for outputting an OR output of an external interrupt factor and an internal interrupt factor as an interrupt request signal to an outside and an interrupt request output method of the semiconductor integrated circuit.
2. Description of the Related Art
In some system structures using a semiconductor integrated circuit, an interrupt request signal given from an external interrupt factor is fetched into the semiconductor integrated circuit and OR control with an interrupt request signal given from an internal interrupt factor is carried out therein, and they are thus aggregated into one interrupt request signal and a notification of the interrupt is given to a CPU.
FIG. 5 is a block diagram showing a system structure related to such a conventional interrupt processing. In FIG. 5, 501 denotes a semiconductor integrated circuit which includes an interrupt control circuit 511 for carrying out OR control of an internal or external interrupt factor. 502 denotes a CPU for processing an interrupt request given from the semiconductor integrated circuit 501, and 503 denotes a power supply unit controlled by the CPU 502 and supplying a power to the semiconductor integrated circuit 501. 504 denotes an external interrupt factor unit, and a low active interrupt signal sent from the external interrupt factor unit 504 is input to the semiconductor integrated circuit 501.
The semiconductor integrated circuit 501 is divided into an internal power source section 505a and an I/O power source section 505b by a power voltage supplied to the circuit, and is controlled by the CPU 502 and receives independent power supply from the power supply unit 503, respectively.
An input/output terminal cell is arranged in the I/O power source section 505b. 506 denotes an input cell for receiving an internal power source breaking mode signal from the CPU 502 in the power down mode of the semiconductor integrated circuit 501, 507 denotes an output cell for transmitting an interrupt request signal to the CPU 502, and 508 denotes an input cell for receiving an interrupt request signal generated from the external interrupt factor unit 504.
Since the internal power source section 505a and the I/O power source section 505b are operated at different voltages, a signal is transferred between a logic arranged in the internal power source section 505a and a logic arranged in the I/O power source section 505b through a voltage level shifter circuit. For this reason, the output cell 507 and the input cell 508 include voltage level shifter circuits 509 and 510, respectively.
The internal power source breaking mode signal is “1” active and the CPU 502 sets the same signal to be “1”, thereby reporting the breaking of an internal power source to the semiconductor integrated circuit 501 in advance. Prior to a transition to the power down mode of the semiconductor integrated circuit 501, the CPU 502 first sets the internal power source breaking mode signal to be sent to the input cell 506 of the semiconductor integrated circuit 501 to be “1” and the logic of the output cell of the I/O power source section 505b is fixed to either of stable directions of “H” and “L”.
The output cell 507 is fixed to “H” in an internal power source breaking mode.
Then, the CPU 502 issues the internal power source breaking instruction of the semiconductor integrated circuit to the power supply unit 503, and the power supply unit 503 breaks a power source for the internal power source section 505a of the semiconductor integrated circuit 501. By such a serial procedure, the semiconductor integrated circuit 501 is subjected to a transition to the power down mode.
An interrupt control circuit 511 is provided in the internal power source section 505a, and carries out OR control of an external interrupt factor 512 output from the external interrupt factor unit 504 and transmitted to the internal power source section 505a through the input cell 508 and an internal interrupt factor group 513 generated in another circuit of the internal power source section 505a, and finally aggregates them into one interrupt request signal 514 and gives a notification to the CPU 502 through the output cell 507.
A technique for treating an interrupt signal related to the power down mode transition has been disclosed in Patent Document 1.
[Patent Document 1]
JP-A-9-44278 gazette
[Problems that the Invention is to Solve]
In the structure according to the conventional embodiment, however, the internal power source section is shut-off in the power down mode of the semiconductor integrated circuit, and at the same time, the interrupt control circuit provided in the internal power source section becomes inoperable and the output cell of the interrupt request signal which is provided in the I/O power source section is fixed to “H”. Even if an interrupt request is given from the external interrupt factor to the input cell of the semiconductor integrated circuit, therefore, the notification cannot be sent to the CPU.
In this case, the notification, to the CPU, of the interrupt request given from the external interrupt factor is stopped while the semiconductor integrated circuit is set in the power down mode. If the notification cannot be stopped, an interrupt request signal input for the external interrupt factor is to be provided on the CPU side separately from the input of the interrupt request signal sent from the output cell of the semiconductor integrated circuit.